The present invention relates to a semiconductor memory device using a dynamic memory cell.
Conventionally, in a dynamic RAM having a CMOS structure, in order to prevent data destruction which occurs when minority carriers generated in external circuits, such as an address buffer or a data I/O buffer, are absorbed in a memory node (capacitor) of a memory cell, the memory cell is formed in a well region so as to be insulated from the external circuits.
FIG. 1 is a pattern plan view of a dynamic RAM having the above structure. P-type well regions 2 and 3 are formed in n-type semiconductor substrate 1. Memory cell array 4, dummy cell 5, and bit line driver 6 are formed in region 2. Driver 6 comprises a bit line precharger, a bit line equalizer, a sense amplifier, and a column selection switching circuit. External circuit 7 having a CMOS structure is formed in region 3 and substrate 1.
When array 4 is insulated from circuit 7 as described above, the memory cell is not adversely affected by minority carriers.
However, even if the above arrangement is adopted, data destruction sometimes still occurs. This is because a p-n junction between p-type region 2 and an n-type diffusion layer formed in region 2 is forwardly biased to generate minority carriers, due to coupling between a bit line, a word line, and control signal lines for driving driver 6, and region 2 in which array 4 is formed.
Another reason for the occurrence of data destruction is the generation of minority carriers upon operation of driver 6 formed together with array 4 in region 2. This is because a MOS transistor is often operated in a pentode region to generate a large number of minority carriers in driver 6 which comprises the bit line precharger, the bit line equalizer, the sense amplifier, and the column selection switching circuit.
Generation of minority carriers due to coupling between the signal lines and region 2 can be prevented by biasing region 2 below VSS, e.g., -3 V or less. However, well potential varies in accordance with an operation of driver 6. Therefore, if a well bias is applied, the power consumption of a biasing circuit greatly increases. In addition, since application of the well bias increases the threshold voltage of, for example, an n-channel MOS transistor in the sense amplifier, by way of a so-called substrate biasing effect, the current drive capacity of the sense amplifier is reduced, which leads to a reduction in the operating speed of the memory cell.
FIG. 2 shows a circuit arrangement in which the dynamic memory cell of FIG. 1 is applied to a dynamic memory cell of an intermediate potential precharging type.
In FIG. 2, reference symbols DWL0 and DWL1 denote dummy word lines; WL0, WL1, . . . , WL0a, and WL1a, word lines; EQ, an equalizing control line; SE and SE, sense amplifier control lines; BL and BL, bit lines; Qa and Qb, n-channel MOS transistors constituting dummy cell 5; Cs0 to Cs3, data storing capacitors of memory cell array 4; Q0, Q1, Q0a, and Q1a, n-channel MOS transistors for a transfer gate of array 4; QA and QB, n-channel MOS transistors for bit line precharger 171; QC, an n-channel MOS transistor for bit line equalizer 172; QC1 and QC2, n-channel MOS transistors constituting column selection switching circuit 173; Bu, I/O buffer 181 constituting external circuit 7; QD and QE, p-channel MOS transistors constituting sense amplifier SA; and QF and QG, n-channel MOS transistors constituting amplifier SA.
As stated above, dummy cell 5 is constituted by a pair of transistors Qa and Qb. The source and drain of transistor Qa are commonly connected to line BL, those of transistor Qb are commonly connected to line BL, and the gates of these transistors are connected to lines DWLa and DWLb, respectively.
Array 4 is constituted by a pair of transistors Q0 and Q1, a pair of transistors Q0a and Q1a, and capacitors Cs0 to Cs3. One of the source and drain of each of transistors Q0 and Q0a is connected to line BL, one of the source and drain of each of transistors Q1 and Q1a is connected to line BL, and the gate of each transistor is connected to a corresponding one of lines WL0, WL1, WL0a, and WL1a. The other of the source and drain of each of transistors Q0, Q1, Q0a, and Q1a is connected to an end of a corresponding one of capacitors Cs0 to Cs3. The other ends of capacitors Cs0 to Cs3 are connected to a predetermined potential.
Conventionally, in order to drive such a dummy cell type dynamic memory cell, word lines WL and dummy word lines DWL are driven by signals of the same phase. This operation will now be described below, with reference to a timing chart shown in FIG. 3.
First, when line EQ is set at level "H", transistors QA and QB of precharger 171 and transistor QC of equalizer 172 are turned on. When transistors QA, QB, and QC are turned on, lines BL and BL are precharged to a potential of 1/2 VDD. When precharging is completed, line EQ is set at level "L", and lines BL and BL are floated. Thereafter, one of the word lines, e.g., line WL0, is set at level "H", and transistor Q0 of a memory cell connected to line BL is turned on. When line BL is set at level "H", line DWLb is set at level "H", and transistor Qb of a dummy cell connected to line BL is turned on. When line WL0 is set at level "H" and transistor Q0 of the memory cell is turned on, potential difference .DELTA.Vsig corresponding to cell data is generated between lines BL and BL. Therefore, when line SE is set at level "H" and line SE is set at level "L", amplifier SA is activated. As a result, difference .DELTA.Vsig is amplified by amplifier SA, to read out data.
On the other hand, when line WL1 is set at level "H", line DWLa is set at level "H", and data of the memory cell connected to line BL is read out.
As has been described above, in the case of the conventional memory cell, the dummy word line which is connected to the bit line opposite to that connected to the memory cell selected by the word line is activated. Signal waveforms of the word lines and the dummy word lines are as shown in FIG. 3. For example, the waveform of line WL0 is the same as that of line DWLa, as is the waveform of line WL1. Note that a voltage value obtained when the word line is selected is different from that obtained when the dummy word line is selected.
In the intermediate potential precharging type dynamic memory cell driven as described above, noise is generated in lines BL and BL, in accordance with the capacitive coupling state between lines WL and DWL.
FIG. 4 is an equivalent circuit diagram showing various parasitic capacitances generated when the dynamic memory cell of FIG. 2 is driven in accordance with the timing chart of FIG. 3. Gate capacitance CG of the memory cell and wiring capacitance CW of wiring between bit and word lines BL and WL are connected between lines BL and WL. Wiring capacitance CDW of wiring between bit and dummy word lines BL and DWL is connected therebetween.
Wiring capacitance CW of wiring between lines BL and WL is connected therebetween. Gate capacitance CDG of the dummy cell and wiring capacitance CDW of wiring between lines BL and DWL are connected between lines BL and DWL.
Gate-substrate capacitance CB and word line-substrate capacitance CWL,B of the memory cell are connected between line WL and the substrate. Gate-substrate capacitance CDB and dummy word line-substrate capacitance CDWL,B are connected between line DWL and the substrate.
Since such parasitic capacitances exist, assuming that the amplitude of a signal applied to line WL is VWL (note that VWL&gt;VDD where VDD is a power source potential) and the amplitude of a signal applied to line DWL is VDWL, potentials .DELTA.Vcoup1 and .DELTA.Vcoup2 of noise generated in lines BL and BL are represented by the following equations: EQU .DELTA.Vcoup1=((CG+CW).multidot.VWL+CDW.multidot.VDWL)/CBL (1) EQU .DELTA.Vcoup2=(CW.multidot.VEL+(CDG+CDW).multidot.VDWL)/CBL (2)
where CBL is the parasitic capacitance respectively of lines BL and BL.
The timing chart of FIG. 3 shows a case wherein noise potential .DELTA.Vcoup2 is generated in line BL. The amplitudes of potentials .DELTA.Vcoup1 and .DELTA.Vcoup2 become about 100 mV at maximum, thereby degrading the sensitivity of the sense amplifier. As a result, such characteristics as the pause characteristic and the power source voltage margin are degraded.
As has been described above, in the case of the conventional device, since the potential of the word line to be selected and that of the dummy word line are varied in the same direction at the same time, a large amount of noise is generated in the bit lines and the substrate, thereby degrading such characteristics as the pause characteristic and the power source margin.